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Physical Dimensions
2X
0.10 C
2.00
A
B
6
1.00
(0.20)
4
No Traces allowed in
this Area
2.00
1.05
1.35
2.30
(0.475)
Pin #1 location
TOP VIEW
2X
0.10 C
0.65 TYP
1
3
0.40 TYP
RECOMMENDED LAND PATTERN OPT 1
0.8 MAX
0.10 C
(0.20)
0.08 C 0.05
0.00
SEATING
PLANE
SIDE VIEW
0.15
C
0.45
6X 0.33
PIN #1 IDENT
0.20
1.00
0.80
1
3
0.50
0.30
0.61
0.51
6
1.00
0.20
4
0.50
1.05
0.95
1.05
1.35
0.66 2.30
6X
0.65
6
1.30
4
0.35
0.25
0.10
C A B
0.65 TYP
1
3
0.40 TYP
0.05
C
RECOMMENDED LAND PATTERN OPT 2
BOTTOM VIEW
A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION
MO-229 DATED AUG/2003
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. DRAWING FILENAME: MKT-MLP06Lrev3.
Figure 20. 6-Lead, Molded Leadless Package (MLP), Dual, Non-JEDEC, 2mm Square, Single-Tied DAP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/ .
? 2012 Fairchild Semiconductor Corporation
FR011L5J ? Rev. C3
11
www.fairchildsemi.com
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